Performance Analyzing of CMOS Gates by Sub Clocking Method Using Cadence Tools
نویسندگان
چکیده
Reducing the power consumed by the device is the emerging trend. The aim of this project is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. In this paper there are two modes of operation are implemented.1. Half mode operation, 2. Full mode operation. This mode of operation are implemented in the two designing method. Design-1: pMOS and nMOS are connected at the header side of the standard CMOS circuit.Design-2: pMOS and nMOS are connected at the header side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the unit.
منابع مشابه
Dual-VDD, Single-Frequency Clocking Methodology for System on Chip
Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relativ...
متن کاملAdiabatic CMOS: Limits of Reversible Energy Recovery and First Steps for Design Automation
Standard CMOS technology discards all signal energy during every switching cycle, leading to heat generation that limits the operating speed and the achievable computing performance. Energy-recovery schemes avoid the heat generation, but are often burdened with the cost of significant increase in system complexity and the lack of automated design tools. In this paper, we propose to implement ad...
متن کاملModeling and Comparative Analysis of Logic Gates for Adder and Multiplier Applications -A VLSI based approach
The logic gates are the fundamental building blocks of VLSI and embedded applications. These gates can be designed using several design techniques and implemented at different levels of architectures. This paper focuses on design and evaluate the performance of logic gates used in the Adders and Multiplier using various design technique like CMOS design GDI design and PTL design. These differen...
متن کاملDesign and Analysis of Register Element for Low Power Clocking System
The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...
متن کاملDesign of an Ultra Low Power Clock Gating D Flip-Flop Using Quasi-Static Energy Recovery Logic
This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...
متن کامل